Positioning/routing represents a major effort in designing integrated circuits. A positioning/routing operation positions the different electronic components of an integrated circuit and routes the electrical connections by metal conductors or conductors made of a highly conductive material. For digital circuits, the positioning/routing process may be achieved entirely or partially by using software commonly known as a silicon compiler. The silicon compiler can carry out the entire positioning/routing of an integrated circuit in compliance with the constraints dictated by circuit designers. The silicon compiler also takes into account the positioning algorithms necessary for the software.
The work required for positioning/routing of a global clock circuit primarily lies in making the choices that the machine cannot make or in revising the constraints provided by the software so the machine can carry out the computation. To reduce the computation and development times, a subdivision of the integrated circuit into functional blocks is carried out. These functional blocks are tested individually before being assembled on the integrated circuit. This makes it possible to have complex functional blocks, e.g., a microprocessor core, that are common to several integrated circuits.
The term "large-sized integrated circuit" is defined as an integrated circuit whose dimensions are such that the delay due to the propagation of an electrical signal on a conductive line extending from one side of the integrated circuit to the other is not negligible, particularly when the integrated circuit operates at high frequencies. During the design of an integrated circuit at the functional level, those skilled in the art generally assume that the clock signals reach all the elements of an integrated circuit synchronously. However, to insure efficient operation of the integrated circuit, those skilled in the art must take account of possible phase delays in the clock signal when they carry out a time balance study of the integrated circuit. The propagation times on a conductive line in an integrated circuit primarily depends on three parameters which, for a given technology, are the length of the conductor, the width of the conductor and the number of elements that are connected to this line.
In large-sized integrated circuits, the originally stipulated tolerance value may be erroneous after the routing of the comprehensive or total clock circuit, thus reducing the performance characteristics of the integrated circuit. An increase in the constraints during the routing of the clock circuit may result, in certain cases, in an impossibility of automatic routing because the comprehensive or total clock circuit is the most difficult circuit to route. In certain cases, non-compliance with time-related performance characteristics may make an integrated circuit useless or unusable. These problems of the total distribution of clock signals are known to those skilled in the art who have methods available to cope with them.
A first method includes over-valuing the possible delays. This approach provides circuit designs that are faster than actually needed. This amounts to designing circuits that are over-sized and, therefore, costly. A second method includes achieving maximum control over the delays introduced by the propagation of the clock signal. This second method takes the form of several different techniques for the positioning/routing of the clock signal circuit designed to reduce the phase differences on a clock signal between any two points of an integrated circuit.
A first technique is shown in FIG. 1. This first technique includes making a metal grid to distribute the clock signal throughout the circuit. The metal grid has a first effect which is to make the capacitance values due to the elements that receive the clock signal negligible as compared with the parasitic capacitance of the grid. A second effect produced by this metal grid is to reduce the resistance of the conductors which distribute the clock signal. The combination of these first and second effects is that there is a small phase difference throughout the circuit.
However, the metal grid has two drawbacks. A first drawback is related to its grid structure which uses an entire layer of metal, or a very large part of the metal layer, thus rendering the layer of metal unusable for making other connections. A second drawback is related to the compensation of the phase differences which tends to considerably increase the parasitic capacitance of the metal grid since the parasitic capacitance is dependent upon the surface area of the integrated circuit. This substantial parasitic capacitance prompts high power consumption by the integrated circuit.
A second technique is shown in FIG. 2. This second technique includes positioning identical clock signal amplifiers throughout the surface of the integrated circuit. These identical clock signal amplifiers receive all the clock signals by a tree-like distribution network such that all the clock signal amplifiers receive the clock signal with the same delay. Each clock signal amplifier then distributes the signal on a small surface of the integrated circuit in which the propagation times on the conductive lines are considered to be negligible. Each clock signal amplifier has an output stage proportional to the number of elements that are connected thereto.
A first drawback of this second technique is the need to position all the clock signal amplifiers on the integrated circuit before positioning the other elements of the integrated circuit. A second drawback arises out of the elimination of one or more clock signal amplifiers that are unnecessary and/or inconvenient. As a result, for example, the tree-like structure is unbalanced and the clock signal amplifiers no longer receive the clock signal in phase.
A third technique, shown in FIG. 3, combines the above two techniques. The surface of the integrated circuit is divided into several small surfaces of identical dimensions, with each small surface being covered with a metal grid. The metal grids are then connected to a clock distribution network with a tree-like structure. This enables a reduction of the consumption of the metal grids which, since they are smaller-sized, can use finer conductors and thus reduce the parasitic capacitance of each grid. Furthermore, if a zone of the integrated circuit does not need a clock signal, the metal grids may be eliminated. As compared with the second technique, the clock signal amplifiers are positioned between the different locations of the grids providing flexibility to position the other elements of the integrated circuit. Although reduced, the drawbacks of the first and second techniques are still present.
A fourth technique, shown in FIG. 4, includes achieving a dynamic compensation for the delays on the clock signal on the basis of measurement points. This fourth technique can be combined with the second and third techniques and enables a partial rebalancing of a tree-like structure. However, the compensation only shifts the phase imbalance and cannot totally compensate for it.